Senior FPGA Engineer - Hybrid (VHDL/Verilog)

The American Society of Civil Engineers is looking for a Senior / Principal FPGA Engineer based in the United Kingdom. The role involves creating robust VHDL-based designs and requires at least 5 years of FPGA development experience using VHDL or Verilog. Familiarity with Mentor Graphics tools and Xilinx design flows is essential. The position offers a hybrid work model, approximately £88 per hour, and includes overtime. Interested candidates can apply directly or contact Lukas via WhatsApp or phone.