Staff Digital Design Engineer

At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

This is an outstanding opportunity for an experienced engineer passionate about circuit power optimization to apply their skills to high-speed SerDes (Serializer/Deserializer) systems. As part of a team, you will evaluate and optimize advanced DSP algorithms and circuits for 200+Gbps SerDes for lowest static and dynamic power consumption. Your work will directly impact the performance of AMD's next-generation connectivity solutions for markets such as data center networking and wireless telecommunications.

You are a collaborative team player with deep expertise in digital circuit power analysis, optimization and practical implementation. You communicate effectively across hardware and algorithm teams, and thrive in a fast-paced, cross-site environment. Your analytical skills and commitment to continuous learning enable you to solve complex problems with novel solutions, elevating the team's capabilities.

• Collaborate with architects, hardware engineers and verification engineers to define, refine and implement low power DSP features for cutting-edge and next-generation SerDes transceivers
• Model and evaluate equalization, filtering and sequence detection algorithms for power efficiency
• Contribute to RTL development, using front-end ASIC tools to ensure the highest quality code
• Contribute to power testcase creation with verification engineers
• Develop comprehensive documentation detailing power optimization approaches

• Proven experience in power analysis and optimization of digital logic at advanced process nodes
• Strong background in digital design techniques, RTL (preferably SystemVerilog)
• Experience with PowerArtist and/or PPRTL tools, scripting and flows
• Familiarity with ASIC front-end design tools and flows, in particular vectored power analysis and gate-level simulation
• Familiarity with equalization techniques such as FFE, CTLE, DFE or MLSE and their implementation would be an advantage

BSc or Masters in Electronics, Electrical or Computer Engineering, or related field.

Benefits offered are described:

AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.