Lumai
Oxford, Oxfordshire
The Opportunity Lumai is redefining how the world computes. We are an ambitious, venture-backed UK startup pioneering a breakthrough AI accelerator for data centers which uses 3D optical compute. Our radical technology uses light to perform computation at orders of magnitude faster speeds and at far greater scales than ever before, all whilst consuming far less energy than traditional approaches. Lumai is unlocking performance and efficiency gains that could transform the economics of AI and compute infrastructure and reshape how intelligence scales globally. If you are passionate about bringing groundbreaking technology to market, and want to be part of a team pushing the boundaries of what is physically possible, Lumai is where you can make it happen. About Lumai Founded in 2022, Lumai is a University of Oxford spinout using optical processing to accelerate large language models (LLMs) and other transformer-based AI systems. The team combines expertise in optical computing, machine learning, and physics. Lumai has already secured over $15 million in investment from leading deep-tech investors like Constructor Capital, IP Group, PhotonVentures and government grants, and is scaling rapidly to deploy the fastest optical compute currently available globally. The Role We are building custom AI hardware and the full-stack software ecosystem to run it. As our first dedicated MLOps Engineer, you will own the infrastructure that takes models from research to silicon-validated production - designing, building, and operating the pipelines, tooling, and platforms that let our AI and hardware teams move fast without breaking things. This is a high-impact, high-ownership role at the intersection of ML research, compiler stacks, and novel hardware What You'll Do Design and operate end-to-end ML pipelines: data ingest, training, evaluation, quantisation, and deployment onto custom AI accelerator hardware Build and maintain experiment tracking, model registry, and versioning infrastructure (e.g. MLflow, W&B, or equivalent) tuned to our hardware-in-the-loop workflows Own CI/CD for ML: automated testing of model correctness, numerical accuracy, and on-chip performance after every change to models, compilers, or firmware Develop and maintain tooling for benchmarking model inference on custom silicon, including latency, throughput, power, and utilisation metrics Collaborate closely with ML researchers, compiler engineers, and hardware architects to identify and remove bottlenecks across the model-to-chip workflow Instrument and monitor production inference deployments; design alerting and rollback strategies appropriate to hardware-accelerated serving Manage compute resource scheduling across on-premises accelerator clusters and cloud (GPU/CPU) for training and simulation workloads Drive infrastructure-as-code practices: containerisation, orchestration (Kubernetes/Slurm), and reproducible environment management Contribute to the internal developer platform: self-service tooling, documentation, and runbooks that raise engineering productivity across the company What We're Looking For Must-Have 5+ years of software or infrastructure engineering experience, with at least 2 years in an ML or AI-adjacent role Strong Python skills and familiarity with major ML frameworks (PyTorch or JAX); comfortable reading and modifying model code Hands-on experience building and operating ML pipelines in production: data pipelines, training orchestration, evaluation, and serving Experience with experiment tracking and model lifecycle management tools (MLflow, W&B, DVC, or similar) Solid understanding of containerisation (Docker) and orchestration (Kubernetes or Slurm) for distributed compute workloads Infrastructure-as-code mindset: Terraform, Ansible, or equivalent; CI/CD pipelines (GitHub Actions, Jenkins, or similar) Experience with hardware-accelerated compute (CUDA/GPU workflows, profiling, performance tuning) - even if not on custom silicon Strong debugging and observability skills: distributed tracing, logging, metrics dashboards Ability to work effectively in a fast-moving, ambiguous environment where the hardware and software are both being built simultaneously Strong Preference For Experience with custom or novel accelerator hardware (FPGAs, ASICs, NPUs, or research chips) Familiarity with ML compiler stacks: MLIR, LLVM, TVM, XLA, or vendor-specific compilers (NVCC, TensorRT, etc.) Experience with model optimisation techniques: quantisation (INT8/INT4/FP8), pruning, distillation, or mixed-precision training Background in on-chip performance profiling and roofline analysis Exposure to chip bring-up workflows: running early software stacks on pre-silicon simulation or first-silicon hardware Contributions to open-source ML infrastructure or compiler tooling Experience in a deeptech, semiconductor, or hardware startup environment Compensation & Benefits Highly Competitive Salary: We are not saying our salary is a blank check, but let's just say it won't be a source of your stress Share Option Scheme: We are all in this together! We believe in shared success while we build the Lumai of tomorrow Pension Scheme: Plan for retirement with AVIVA Private Health Insurance: We firmly believe that you come first, and a happy you is a healthy you! Look after yourself and your loved ones with AXA Cycle to Work: Spread the cost of a bike, a bike and accessories or just accessories and save on tax L&D Allowance: Stay at the forefront of your field with a £500 annual development budget Subsidised On-site Lunches: Enjoy on-site healthy meals at half the price, as Lumai covers 50% of the cost Holidays: Enjoy some deserved "me time" with 25 days paid holiday (plus bank holidays) per year Socials: Be part of an inclusive community enjoying occasional all-company off-sites, lunches and socials Interview Process Our process is four stages. An initial conversation with our HR team to understand what you want from the role and what we want from it. Two technical sessions with various members of our engineering team. Finally, an HR-team session covering scope, terms, and any final questions. We aim to move fast on candidates we are excited about; expect roughly three to four weeks end to end. Lumai is an equal opportunity employer. We make hiring decisions on merit, scope-fit, and the strength of the working relationship we expect to build with each hire. Applications welcome from candidates of any background. If you are not sure whether you are a fit, send a note anyway.
The Opportunity Lumai is redefining how the world computes. We are an ambitious, venture-backed UK startup pioneering a breakthrough AI accelerator for data centers which uses 3D optical compute. Our radical technology uses light to perform computation at orders of magnitude faster speeds and at far greater scales than ever before, all whilst consuming far less energy than traditional approaches. Lumai is unlocking performance and efficiency gains that could transform the economics of AI and compute infrastructure and reshape how intelligence scales globally. If you are passionate about bringing groundbreaking technology to market, and want to be part of a team pushing the boundaries of what is physically possible, Lumai is where you can make it happen. About Lumai Founded in 2022, Lumai is a University of Oxford spinout using optical processing to accelerate large language models (LLMs) and other transformer-based AI systems. The team combines expertise in optical computing, machine learning, and physics. Lumai has already secured over $15 million in investment from leading deep-tech investors like Constructor Capital, IP Group, PhotonVentures and government grants, and is scaling rapidly to deploy the fastest optical compute currently available globally. The Role We are building custom AI hardware and the full-stack software ecosystem to run it. As our first dedicated MLOps Engineer, you will own the infrastructure that takes models from research to silicon-validated production - designing, building, and operating the pipelines, tooling, and platforms that let our AI and hardware teams move fast without breaking things. This is a high-impact, high-ownership role at the intersection of ML research, compiler stacks, and novel hardware What You'll Do Design and operate end-to-end ML pipelines: data ingest, training, evaluation, quantisation, and deployment onto custom AI accelerator hardware Build and maintain experiment tracking, model registry, and versioning infrastructure (e.g. MLflow, W&B, or equivalent) tuned to our hardware-in-the-loop workflows Own CI/CD for ML: automated testing of model correctness, numerical accuracy, and on-chip performance after every change to models, compilers, or firmware Develop and maintain tooling for benchmarking model inference on custom silicon, including latency, throughput, power, and utilisation metrics Collaborate closely with ML researchers, compiler engineers, and hardware architects to identify and remove bottlenecks across the model-to-chip workflow Instrument and monitor production inference deployments; design alerting and rollback strategies appropriate to hardware-accelerated serving Manage compute resource scheduling across on-premises accelerator clusters and cloud (GPU/CPU) for training and simulation workloads Drive infrastructure-as-code practices: containerisation, orchestration (Kubernetes/Slurm), and reproducible environment management Contribute to the internal developer platform: self-service tooling, documentation, and runbooks that raise engineering productivity across the company What We're Looking For Must-Have 5+ years of software or infrastructure engineering experience, with at least 2 years in an ML or AI-adjacent role Strong Python skills and familiarity with major ML frameworks (PyTorch or JAX); comfortable reading and modifying model code Hands-on experience building and operating ML pipelines in production: data pipelines, training orchestration, evaluation, and serving Experience with experiment tracking and model lifecycle management tools (MLflow, W&B, DVC, or similar) Solid understanding of containerisation (Docker) and orchestration (Kubernetes or Slurm) for distributed compute workloads Infrastructure-as-code mindset: Terraform, Ansible, or equivalent; CI/CD pipelines (GitHub Actions, Jenkins, or similar) Experience with hardware-accelerated compute (CUDA/GPU workflows, profiling, performance tuning) - even if not on custom silicon Strong debugging and observability skills: distributed tracing, logging, metrics dashboards Ability to work effectively in a fast-moving, ambiguous environment where the hardware and software are both being built simultaneously Strong Preference For Experience with custom or novel accelerator hardware (FPGAs, ASICs, NPUs, or research chips) Familiarity with ML compiler stacks: MLIR, LLVM, TVM, XLA, or vendor-specific compilers (NVCC, TensorRT, etc.) Experience with model optimisation techniques: quantisation (INT8/INT4/FP8), pruning, distillation, or mixed-precision training Background in on-chip performance profiling and roofline analysis Exposure to chip bring-up workflows: running early software stacks on pre-silicon simulation or first-silicon hardware Contributions to open-source ML infrastructure or compiler tooling Experience in a deeptech, semiconductor, or hardware startup environment Compensation & Benefits Highly Competitive Salary: We are not saying our salary is a blank check, but let's just say it won't be a source of your stress Share Option Scheme: We are all in this together! We believe in shared success while we build the Lumai of tomorrow Pension Scheme: Plan for retirement with AVIVA Private Health Insurance: We firmly believe that you come first, and a happy you is a healthy you! Look after yourself and your loved ones with AXA Cycle to Work: Spread the cost of a bike, a bike and accessories or just accessories and save on tax L&D Allowance: Stay at the forefront of your field with a £500 annual development budget Subsidised On-site Lunches: Enjoy on-site healthy meals at half the price, as Lumai covers 50% of the cost Holidays: Enjoy some deserved "me time" with 25 days paid holiday (plus bank holidays) per year Socials: Be part of an inclusive community enjoying occasional all-company off-sites, lunches and socials Interview Process Our process is four stages. An initial conversation with our HR team to understand what you want from the role and what we want from it. Two technical sessions with various members of our engineering team. Finally, an HR-team session covering scope, terms, and any final questions. We aim to move fast on candidates we are excited about; expect roughly three to four weeks end to end. Lumai is an equal opportunity employer. We make hiring decisions on merit, scope-fit, and the strength of the working relationship we expect to build with each hire. Applications welcome from candidates of any background. If you are not sure whether you are a fit, send a note anyway.
Lumai
Oxford, Oxfordshire
The Role We are looking for a System Architect who thinks in AI first and hardware second. You will own the architectural vision that bridges our AI workload requirements with our silicon and software execution. This is not a role for someone who designs chips and then asks what AI runs on them - it's a role for someone who deeply understands AI models, inference and training pipelines, and then works backwards to define the hardware and software systems that serve them best. You will sit at the intersection of leadership, hardware engineering, and software engineering - translating high-level product strategy into concrete architectural decisions and ensuring all three teams are aligned, unblocked, and pulling in the same direction. What You'll Do Architecture & Technical Leadership Define and own the end-to-end system architecture, from AI workload characterisation through to chip microarchitecture trade-offs and software stack interfaces Drive architectural decisions by starting with AI model and operator analysis - identifying compute, memory bandwidth, data movement, and sparsity patterns that constrain and shape the hardware design Develop and maintain architectural specifications, performance models, and design documents that serve as the single source of truth across teams Evaluate architectural trade-offs (latency vs. throughput, on-chip vs. off-chip memory, dataflow strategies, precision formats) with a quantitative, workload-grounded methodology Stay current with the frontier of AI research (model architectures, training techniques, inference optimisations) and translate emerging trends into architectural foresight Cross-functional Coordination Act as the primary technical bridge between the leadership team, hardware engineering, and software engineering - ensuring that decisions made in one domain are properly communicated, challenged, and integrated in others Partner with the leadership team to translate business goals and product roadmap into architectural requirements and phased execution plans Work closely with the hardware team to ensure microarchitectural decisions are grounded in realistic AI workload demands; push back constructively when hardware-centric thinking diverges from AI requirements Collaborate with the software team to define clean hardware/software interfaces, programming models, and runtime abstractions that make the hardware genuinely usable for AI practitioners Facilitate architectural reviews and design discussions that create shared understanding rather than siloed decision-making Execution & Delivery Identify and resolve cross-team dependencies and ambiguities early, before they become schedule risks Define and track key architectural metrics and milestones throughout the chip development lifecycle (pre-RTL through tape-out and post-silicon validation) Support benchmarking and performance analysis efforts, helping teams understand where the system delivers against AI workload targets and where it falls short What We're Looking For Must-Have Deep, hands on understanding of modern AI/ML workloads - transformer architectures, convolutional networks, recommendation systems, or similar - including their compute and memory access patterns Proven experience defining system or chip architecture in the context of AI/ML acceleration (inference, training, or both) Ability to build and use analytical performance models (roofline models, memory bandwidth analysis, cycle accurate estimates) to guide architectural decisions Strong communication skills with the ability to adapt technical depth for leadership, hardware engineers, and software engineers alike Experience working across hardware and software boundaries - comfortable discussing ISA design, compiler interfaces, and runtime scheduling as well as datapath microarchitecture Suitable University education and/or practical experience Strong Preference For Experience at an AI chip startup, AI hardware team at a major tech company (e.g. Google TPU, Meta MTIA, AWS Trainium/Inferentia, Tesla Dojo), or a leading fabless semiconductor company Familiarity with AI compiler stacks (MLIR, XLA, TVM, Triton) and how they interact with hardware architecture decisions Understanding of chip development processes: RTL design, physical design constraints, and post silicon bring up Experience with or exposure to on device / edge inference as well as datacenter scale deployments Track record of influencing architectural direction through written specs and data driven arguments rather than authority alone What Success Looks Like In your first 90 days, you will have audited the current architectural approach against a defined set of target AI workloads, identified the top architectural risks to schedule and performance, and established a working rhythm with the HW and SW leads. Within six months, you will be the person who others come to when a cross team decision needs an owner - and the one who keeps the architecture honest against the AI workloads we are building for. Compensation & Benefits Highly Competitive Salary: We are not saying our salary is a blank check, but let's just say it won't be a source of your stress Share Option Scheme: We are all in this together! We believe in shared success while we build the Lumai of tomorrow Pension Scheme: Plan for retirement with AVIVA Private Health Insurance: We firmly believe that you come first, and a happy you is a healthy you! Look after yourself and your loved ones with AXA Cycle to Work: Spread the cost of a bike, a bike and accessories or just accessories and save on tax L&D Allowance: Stay at the forefront of your field with a £500 annual development budget Subsidised On site Lunches: Enjoy on site healthy meals at half the price, as Lumai covers 50% of the cost Holidays: Enjoy some deserved "me time" with 25 days paid holiday (plus bank holidays) per year Socials: Be part of an inclusive community enjoying occasional all company off sites, lunches and socials Lumai is an equal opportunity employer. We make hiring decisions on merit, scope fit, and the strength of the working relationship we expect to build with each hire. Applications welcome from candidates of any background. If you are not sure whether you are a fit, send a note anyway.
The Role We are looking for a System Architect who thinks in AI first and hardware second. You will own the architectural vision that bridges our AI workload requirements with our silicon and software execution. This is not a role for someone who designs chips and then asks what AI runs on them - it's a role for someone who deeply understands AI models, inference and training pipelines, and then works backwards to define the hardware and software systems that serve them best. You will sit at the intersection of leadership, hardware engineering, and software engineering - translating high-level product strategy into concrete architectural decisions and ensuring all three teams are aligned, unblocked, and pulling in the same direction. What You'll Do Architecture & Technical Leadership Define and own the end-to-end system architecture, from AI workload characterisation through to chip microarchitecture trade-offs and software stack interfaces Drive architectural decisions by starting with AI model and operator analysis - identifying compute, memory bandwidth, data movement, and sparsity patterns that constrain and shape the hardware design Develop and maintain architectural specifications, performance models, and design documents that serve as the single source of truth across teams Evaluate architectural trade-offs (latency vs. throughput, on-chip vs. off-chip memory, dataflow strategies, precision formats) with a quantitative, workload-grounded methodology Stay current with the frontier of AI research (model architectures, training techniques, inference optimisations) and translate emerging trends into architectural foresight Cross-functional Coordination Act as the primary technical bridge between the leadership team, hardware engineering, and software engineering - ensuring that decisions made in one domain are properly communicated, challenged, and integrated in others Partner with the leadership team to translate business goals and product roadmap into architectural requirements and phased execution plans Work closely with the hardware team to ensure microarchitectural decisions are grounded in realistic AI workload demands; push back constructively when hardware-centric thinking diverges from AI requirements Collaborate with the software team to define clean hardware/software interfaces, programming models, and runtime abstractions that make the hardware genuinely usable for AI practitioners Facilitate architectural reviews and design discussions that create shared understanding rather than siloed decision-making Execution & Delivery Identify and resolve cross-team dependencies and ambiguities early, before they become schedule risks Define and track key architectural metrics and milestones throughout the chip development lifecycle (pre-RTL through tape-out and post-silicon validation) Support benchmarking and performance analysis efforts, helping teams understand where the system delivers against AI workload targets and where it falls short What We're Looking For Must-Have Deep, hands on understanding of modern AI/ML workloads - transformer architectures, convolutional networks, recommendation systems, or similar - including their compute and memory access patterns Proven experience defining system or chip architecture in the context of AI/ML acceleration (inference, training, or both) Ability to build and use analytical performance models (roofline models, memory bandwidth analysis, cycle accurate estimates) to guide architectural decisions Strong communication skills with the ability to adapt technical depth for leadership, hardware engineers, and software engineers alike Experience working across hardware and software boundaries - comfortable discussing ISA design, compiler interfaces, and runtime scheduling as well as datapath microarchitecture Suitable University education and/or practical experience Strong Preference For Experience at an AI chip startup, AI hardware team at a major tech company (e.g. Google TPU, Meta MTIA, AWS Trainium/Inferentia, Tesla Dojo), or a leading fabless semiconductor company Familiarity with AI compiler stacks (MLIR, XLA, TVM, Triton) and how they interact with hardware architecture decisions Understanding of chip development processes: RTL design, physical design constraints, and post silicon bring up Experience with or exposure to on device / edge inference as well as datacenter scale deployments Track record of influencing architectural direction through written specs and data driven arguments rather than authority alone What Success Looks Like In your first 90 days, you will have audited the current architectural approach against a defined set of target AI workloads, identified the top architectural risks to schedule and performance, and established a working rhythm with the HW and SW leads. Within six months, you will be the person who others come to when a cross team decision needs an owner - and the one who keeps the architecture honest against the AI workloads we are building for. Compensation & Benefits Highly Competitive Salary: We are not saying our salary is a blank check, but let's just say it won't be a source of your stress Share Option Scheme: We are all in this together! We believe in shared success while we build the Lumai of tomorrow Pension Scheme: Plan for retirement with AVIVA Private Health Insurance: We firmly believe that you come first, and a happy you is a healthy you! Look after yourself and your loved ones with AXA Cycle to Work: Spread the cost of a bike, a bike and accessories or just accessories and save on tax L&D Allowance: Stay at the forefront of your field with a £500 annual development budget Subsidised On site Lunches: Enjoy on site healthy meals at half the price, as Lumai covers 50% of the cost Holidays: Enjoy some deserved "me time" with 25 days paid holiday (plus bank holidays) per year Socials: Be part of an inclusive community enjoying occasional all company off sites, lunches and socials Lumai is an equal opportunity employer. We make hiring decisions on merit, scope fit, and the strength of the working relationship we expect to build with each hire. Applications welcome from candidates of any background. If you are not sure whether you are a fit, send a note anyway.