OLIX

The Role As an Architect/Staff Embedded Software Engineers, you will be the foremost technical authority on hardware-software integration across the DX-1, spanning the ASIC, BMC, and photonic interconnect fabric, from pre-silicon through post-silicon and into sustainment engineering. We are looking for experienced Architect, Staff, and Principal-level engineers who will help shape OLIX's direction through systems thinking and deep technical expertise. You will partner closely with the Director of Software Engineering to define the technical direction of the organization, establish architectural standards, and make the critical technical decisions that determine how the hardware-software boundary is defined. You bring exceptional depth across the full stack, the judgment to identify what matters most and why, and the ability to influence and align engineering teams without relying on formal authority. You are comfortable navigating complex technical tradeoffs, driving cross-functional collaboration, and ensuring that system architecture supports both current requirements and future scalability. Responsibilities Own the technical direction for your team. Partner with the Engineering Manager to set technical direction within the team's scope, and take ownership of the architectural decisions that shape how the team builds and operates. Translate priorities into execution. Work with the Engineering Manager to break down complex technical problems into concrete plans, and ensure the team is building the right things in the right way. Hold the technical bar. Define the principles, interface contracts, and standards the team builds to - whether that's firmware interfaces, ASIC validation methodology, or interconnect fabric integration - and ensure they are applied consistently. Make the hard calls in your domain. Own technical decision making within your area: BSP and firmware architecture, ASIC validation methodology, BMC platform design, or interconnect fabric integration - depending on your focus. Drive alignment within the team. Build shared understanding across engineers through rigour, clarity, and well reasoned technical decisions. Collaborate with adjacent teams where your work has dependencies. Own the full lifecycle within your domain. Lead technically across pre silicon, post silicon, and sustainment - from emulation and bring up through to production reliability and field issue resolution. Raise the level of the team. Support the growth of engineers around you - through code review, design feedback, and sharing technical judgment - as a senior individual contributor who holds the bar high. Skills & Experience Deep expertise across firmware and hardware-software co-development - specifically in one or more of: ASIC bring up and validation, BMC/OpenBMC platform firmware, or high speed SerDes and photonic interconnect bring up. Deep expertise in embedded Linux BSP: Yocto/OpenEmbedded, U Boot or UEFI, device driver development, and device tree authoring for custom silicon platforms. Deep expertise in server management protocols IPMI/IPMB, Redfish, MCTP, PLDM - and low speed peripheral integration (I2C, SPI, UART, CPLD) in a rack scale hardware context. Experience with cycle deterministic or precision timing systems - IEEE 1588 / PTP, SyncE, or White Rabbit Protocol - is a significant advantage. Proven track record delivering complex hardware-software integration architecture that has shipped, across multiple generations in large and fast moving organizations. Track record driving technical outcomes in organisations with high reliability expectations, including robust observability, incident management, and close collaboration with hardware and silicon teams on field issues. Outstanding technical communicator. You can articulate architectural decisions and their consequences clearly to engineers, managers, and senior leadership alike, and write design documents that become the reference point for the organisation. Compensation & Equity Competitive Salary: Commensurate with your experience, skills, and location Equity & Ownership: Meaningful stock options. You're not just joining the mission; you're owning a piece of it Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living-Local Bonus if your residence is within 20 minutes of the office Retirement Benefits: Employer contributed retirement plans to help you build long term financial security. Due to U.S. export control regulations, candidates' eligibility to work at OLIX depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.

OLIX in London seeks an Architect/Staff/Principal engineer to own hardware-software integration from pre-silicon to sustainment, spanning ASIC, BMC, and photonic interconnect fabric. You will partner with the Director of Software Engineering to set architectural direction, define standards, and drive cross functional teams while shaping the company's engineering roadmap. You bring deep firmware and hardware experience, strong communication, and a track record of delivering complex systems in

OLIX is seeking an Infrastructure Manager to build and lead the team responsible for the internal platform used by the entire organization. You will own compute, storage, networking, and CI/CD systems enabling hardware, software, ML, and compiler engineers to build and test daily. The role emphasizes high ownership, setting security standards, and scaling IT operations from the ground up as the company grows, with a focus on maximizing engineering velocity and security.

About OLIX AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance. The Role We are looking for an Infrastructure Manager to build and lead the team responsible for the internal platform our entire organization depends on. You will own the compute, storage, networking, and CI/CD systems that our hardware, software, ML, and compiler engineers use to build, test, and collaborate daily. This is a high-ownership role with the freedom to define our internal infrastructure, security standards, and technical operations from the ground up. You will guide your team to transform slow, manual workflows into fast, reproducible, and genuinely secure systems, while currently holding the reins for our foundational IT operations as the company expands. If you care equally about maximizing engineering velocity, establishing best-in-class security, and building a highly capable technical team, there is a massive amount of impactful work to dig into here. Responsibilities Day to day, you will guide your team and manage the strategic execution of our engineering platform and technical operations. This is a mix of strategic alignment, architectural guidance, and team enablement focused on: Team Leadership & Delivery: Directing the team in building provisioning automation, CI/CD pipelines, internal tooling, network design, and observability systems. Operational & IT Oversight: Ensuring your team effectively supports and unblocks engineers on complex build or connectivity issues, while also steering the broader IT function-including identity management, device fleets, and SaaS administration-as we scale through this current phase of growth. Security Posture: Championing a "secure by default" mindset across all infrastructure, endpoints, and access points. Cross-Functional Collaboration: Partnering closely with engineering leaders (with compiler engineering as an early, demanding customer) to ensure the engineering platform and the wider company environment stay highly coherent and efficient. Skills & Experience Team Leadership & Management: Proven track record of managing, mentoring, and scaling high-performing infrastructure, platform, or DevOps engineering teams. You know how to align technical execution with overarching company goals. Deep Technical Foundation: A strong background as an engineer or architect in cloud computing, storage, and networking. You don't need to write every line of code, but you must be able to hold your own in architectural discussions and guide technical decisions. Developer Productivity & CI/CD: Experience overseeing the design and operation of robust build systems and CI/CD pipelines. Familiarity with the unique infrastructure demands of hardware, ML, or compiler engineering teams is a significant plus. Security & Access Management: Deep understanding of infrastructure security, identity and access management (IAM), and endpoint security. You instinctively build environments that are secure by default without destroying engineering velocity. IT Operations Oversight: Demonstrated ability to manage or oversee foundational IT functions, including device fleet management (MDM), SaaS administration, and corporate networking, particularly in a high-growth environment. From-Scratch Builder Mentality: Experience thriving in an early-stage or rapidly scaling environment. You are comfortable defining strategy, establishing processes, and building a platform from the ground up rather than just maintaining legacy systems. Cross-Functional Communication: Excellent ability to partner with diverse technical leaders across software, hardware, and IT, translating complex operational bottlenecks into clear, executable infrastructure strategies. Compensation & Equity Competitive Salary: Commensurate with your experience, skills, and location Equity & Ownership: Meaningful stock options. You're not just joining the mission; you're owning a piece of it Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living-Local Bonus if your residence is within 20 minutes of the office Retirement Benefits:Employer-contributed retirement plans to help you build long-term financial security. Due to U.S. export control regulations, candidates' eligibility to work at OLIX depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.

A leading technology firm in the UK seeks a Staff FPGA Engineer. This role covers the architecture, design, and direction of FPGA systems for the Optical Tensor Processing Unit (OTPU). The ideal candidate has over 8 years of FPGA experience and will lead design efforts on high-speed systems while mentoring a team. The company offers competitive compensation, equity options, and a £24k Living-Local Bonus for nearby residents. Comprehensive healthcare and 25 days of leave are also included.

OLIX is seeking Architect, Staff & Senior Systems Software Engineers to enhance our DX-1 accelerator. You will design and implement the distributed inference stack, validating system behavior before hardware availability. This role is crucial in optimizing performance across a cutting-edge architecture. The ideal candidate has deep experience in systems software, fluency with PyTorch/JAX integration, and the ability to drive cross-team collaboration. Competitive salary and equity options are offered based on skills.

About OLIX AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack scale co design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance. The Role We're searching for Architect, Staff & Senior Systems Software Engineers to own how our next generation DX 1 accelerator is brought to life as a production inference platform. DX 1 is a dataflow architecture built specifically for decode, deployed in a disaggregated inference environment. Your mission is to make that hardware serve large AI models at rack scale by building and extending the runtime and serving stack that connects PyTorch and JAX down to the metal. This is a whole stack systems role. You'll work where the runtime, the network, and the accelerator meet, partnering closely with hardware, compiler, and modelling teams to optimize serving performance. Your impact is measured not only by what you build but by the leverage you create: the standards you set, the systems and tooling other teams build on, and the direction you shape across the platform. Responsibilities Own the Runtime & Serving Stack: Design, build, and extend the distributed inference and serving stack (e.g. vLLM, SGLang, NVIDIA Dynamo, TensorRT LLM) onto DX 1, rather than treating any layer as a black box. Scale Distributed Inference: Define how inference scales across many accelerators: tensor / pipeline / data parallelism, collective communication patterns, KV cache management and offload, and memory aware scheduling across a disaggregated topology. Engineer for Reliability at Scale: Make distributed inference dependable across failure domains (fault handling, graceful degradation, load balancing, and recovery), and define the observability, tracing, and tooling standards that let teams diagnose problems across the runtime, network, and accelerator rather than through logs alone. Drive Bring Up: Evaluate system behaviour before silicon is fully available (simulation, emulation, FPGA prototyping, analytical modelling), root cause what breaks during bring up, and influence design decisions across hardware and software teams. Set Standards Across Teams: Identify the highest impact systems problems across teams and make sure they get solved; hold and articulate a clear technical bar and raise peers to it through review, pairing, and direct challenge; build leverage through systems, frameworks, and developing senior talent rather than solving everything personally. Shape Direction: Bring structure and clear direction to ambiguous, cross team problems, drive structural improvements with urgency, and shape strategic direction within the platform domain, informed by external research, competitive awareness, and industry connections that help generate talent and partnership pipelines. Skills & Experience Deep experience in systems software, with hands on C/C++ and strong systems fundamentals across the runtime / network / accelerator boundary. Demonstrated ownership of a hard, end to end systems problem, ideally extending a distributed inference / serving stack (vLLM, SGLang, NVIDIA Dynamo, TensorRT LLM) in production, with specifics on what you built or changed and why. Distributed inference at scale: parallelism strategies, collective communication, KV cache and memory management, and reliability across distributed failure domains at cluster scale. Fluency at the framework boundary, connecting accelerators to PyTorch / JAX and serving stacks without treating either as opaque. Whole stack debugging: end to end and timeline tracing, workload replay, and reasoning from architectural constraints (SRAM, host-device latency, KV footprint, memory bandwidth, collective latency) to root cause. Strong, business aware judgment on speed / cost / quality trade offs, and a track record of structured, calm handling of late emerging risk. Excellent communication and the ability to align and influence cross functional teams (hardware, compiler, modelling) without relying on formal authority. Bachelor's degree or higher in computer science, electrical engineering, mathematics, or a related field. Nice to have Experience with dataflow or non GPU accelerator architectures; pre/post silicon bring up on custom hardware (ASIC/FPGA); production observability at scale (hardware counters, Prometheus/Grafana style export, device and cluster views). Adjacent depth is welcome: HPC cluster design, high speed networking, distributed systems, or heterogeneous compute platforms. Compensation & Equity Competitive Salary: Commensurate with your experience, skills, and location Equity & Ownership: Meaningful stock options. You're not just joining the mission; you're owning a piece of it Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living Local Bonus if your residence is within 20 minutes of the office Retirement Benefits: Employer contributed retirement plans to help you build long term financial security. Due to U.S. export control regulations, candidates' eligibility to work at OLIX depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.